File Name: digital system clocking high performance and low power aspects .zip
Clocking is one of the most critical parts of each processor, often determining its performance and largely impacting its power consumption. The clocking subsystem and clocked storage elements in particular are responsible for an increasingly substantial portion of the circuit design improvements needed to accommodate the continuing scaling trends with each processor generation.
Home About My account Contact Us. Earn certifications. Pay attention, respect the material, listen to with Getting your hands on the These kinds of rationale also go for designing software. Oklobdzija, Vladimir M. Stojanovic, Dejan M.
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Library of Congress Cataloging-in-Publication Data is available. We certainly did not think so and we are sure many people today share this view. Indeed, this work started as a simple consulting project for Hitachi America Laboratories in the late s that was not intended to last longer than six months. The objective was to examine several proposed and existing clocked storage elements and decide which one should be used in the new generation of microprocessors Hitachi had on the drawing board at that time.
We finished this work, comparing several existing structures and recommending some improved solutions. However, the answers we provided raised many more questions and left us wondering. Now we feel that there are even more unanswered questions. Thus, we decided to collect our experience into a book and make it available to design engineers, practitioners, academics, managers, and anyone else interested in this aspect of high-performance and low-power digital system design.
Clocking is an important aspect and a centerpiece of digital system design. Not only does it have the highest positive impact on performance and power, but also the highest negative impact on the reliability of an improperly designed system. This is becoming more important, as the clock frequency keeps increasing dramatically as it has been in the last decade. The higher the frequency, the more important are the clock system and clock storage elements, because their effects do not scale proportionally with other features that are benefiting from the rapid technological advances of the past fifty years.
In this book we treat synchronous systems, which we assume will continue to progress in this direction. In reality, we do not know how long this progress will continue. Other ways of timing digital systems are possible, but they have not demonstrated sufficient progress to become a mainstream solution.
We do not pretend to know what the timing of xiii. This book is divided into nine chapters. In Chapter 1 we provide an overview of clocking and how the clocked storage elements fit into the whole picture. The presentation tends to be historic, as we wish to put the development of clocking and clocked storage elements into needed perspective. Some basic definitions are provided and we tie the clock storage elements into the entire digital system, most particularly into clock generation, distribution testability, and control.
Chapter 2 describes clocked storage elements and provides definitions and a clear classification of basic clocked storage elements used in digital systems today. It shows the systematic derivation of flip-flops and sets the stage for the discussion of advanced structures and their performance and energy aspects. The Chapter 3 introduces the timing and energy parameters of the clocked storage elements.
Since the speed required for the operation can always be traded for less energy and vice versa , it is important to tie the two together and place the analysis of performance and power in perspective. Also defined in this chapter is when the data should arrive so that the system operates reliably, as well as the various parameters which affect the power consumption of the system, such as switching activity, voltage scaling, and design style.
Chapter 4 provides a rigorous quantitative analysis of clocking. The choice of the clocked storage elements requires a particular analysis of its effects, and the chapter provides various performance and design trade-offs. The quantitative analysis and derivation of the timing parameters for optimal system performance are also presented, starting with the simple flip-flop-based systems and ending with the complex dual clock-edge clocked systems.
This chapter should provide the reader with the mathematical tools for determining the optimal system parameters for the design. In order to make these points clear, the chapter ends with examples of two advanced clocking techniques: one for high-performance, and other oriented toward the low-power system.
Chapter 5 is dedicated to the issues encountered in designing high-performance systems. Due to the increased effect of clock uncertainties, dealing with the clock skew and jitter and the ability to absorb those unavoidable effects is one of the most important issues in high-performance system design. Since the time boundaries between the stages are more difficult to control precisely, the data from one pipeline stage may take some amount of time from the following one.
This subject, also known as time borrowing is analyzed, and its relation to clock uncertainty absorption is shown. Chapter 6 is dedicated to low-power system design.
It treats the energy issues, in particular, energy reduction. Various ways of achieving low energy per operation, such as supply voltage scaling, reduced signal swing clocking, clock gating, and capturing the data on each transition of the clock signal - dual-edge triggering -are described in this chapter. Clocked storage elements designed with features that minimize energy consumption, such as conditional clocking and conditional precharging, are described and analyzed.
Chapter 7 describes simulation techniques and optimization methods used to properly size the transistors. It discusses the use of the. Most importantly, in this chapter we describe the evaluation setup that should be used in providing a fair comparison between different clocked storage elements and all the miscellaneous issues that affect this comparison.
We provide a script used to simulate clocked storage elements in the Appendix to Chapter 7. This script should serve as a starting point for an engineer who is embarking on this elaborate and tedious undertaking, and we hope it will be useful.
In Chapter 8 we compare the various clocked storage elements that are commonly known or used in systems with outstanding features, such as high performance or low power. This chapter should provide the reader with a feel for the current state of the art in clocked storage elements and present the designer with possible choices for his or her designs.
Finally Chapter 9 describes clocking techniques and clocked storage elements used in representative and well-known microprocessors. It also illuminates various techniques used by microprocessor designers, as well as various design styles and approaches used by different companies that may not be widely known.
This chapter summarizes all the knowledge presented in this book and shows the reader how this knowledge is applied by various practitioners in this highly competitive field. We hope this book will help in achieving even higher microprocessor performance than that available today and set the stage for a number of successful future designs.
Unfortunately much too often it has been taken lightly at the beginning of a design and that viewpoint has proven to be very costly in the long run Wagner Thus, it is not pretentious to dedicate an entire book to this subject. However, this book is limited to the even narrower issue of clocked storage elements CSE , widely known as flip-flops and latches.
The issues dealing with clock generation, frequency stability and control, and clock distribution are too numerous to be discussed in depth in this book and so they are covered only briefly.
The interested reader is referred to the other books dealing with those issues, such as the one by Friedman The importance of clocking has become even more emphasized, as the clock speed is rising rapidly, doubling every three years, as seen in Fig However, the clock uncertainties have not been scaling proportionally with the frequency increase, and an increasingly large portion of the clock cycle has been spent on the clocking overhead.
The ability to absorb clock skew or to make the clocked storage element faster is reflected directly in the enhanced performance, since the performance is directly proportional to the clock frequency of a given system. Such performance improvements are very difficult to obtain using traditional techniques on the architecture or microarchitecture levels. The difficulties are caused by the overhead imposed by the CSE delay, and the clock uncertainties. Thus, setting the clock to the right frequency, and utilizing every available picosecond of the critical path, is increasingly important.
It is our opinion that traditional clocking techniques will reach their limit when the clock frequency reaches the 5 to 10 GHz range. Thus, new ideas and new ways of designing digital systems are needed. We do not pretend to know what the future trend in clocking should 1. Computers built in the past were large and filled several electronic cabinets in large air-conditioned rooms that occupied entire A oors.
They were built from discrete components or used a few large-scale integration LSI chips in the later models. Those systems were clocked at frequencies of about one or a few tens of megahertz, as shown in Table 1. Given the low scale of integration, it was possible to "tune" the clock. This was achieved by either adjusting the length of the wires that distributed the clock signals, or by tuning the various delay elements on the cabinets or the circuit boards, so that the clock signal arrived at every circuit board at approximately the same time.
With the advent of very largescale integration VLSI technology, and increased integration levels, the ability to tune the clock has been greatly diminished. The clock signals are generated and distributed internally within the VLSI chip. Therefore, much of the burden of absorbing clock signal variations at various points on the VLSI chip has fallen on the clocked storage element.
The synchronous system assumes the presence of the. The concept of finite-state machine. This change is determined by the. The function of the clock signal is to provide a reference point in time when the FSM changes from the present, S,,, to the next state, This process is illustrated in Fig In Fig.
In fact, this change is determined by the type of clocked storage element and its functionality. We will be discussing this point in detail later in this book. There are digital systems where this change is not caused by the presence, or more precisely, by a change in the clock signal, but by a change of the data signal, for example. A great deal of research in defining a workable asynchronous system has been done in the last several decades. Recently a microprocessor was designed to operate in an asynchronous manner, and it has been claimed that some small advantages in power consumption were obtained Woods et al.
In spite of that, the practicality and advantage of the asynchronous design has yet to be proven Furber et al. In this book, we limit our discussion to synchronous systems. If we extend the FSM state diagram in time, we obtain an illustration of the pipeline design Fig. In many cases, when dealing with the synchronous design, the delay throughout the logic block is excessive and the signal change cannot propagate to the inputs of the clocked storage elements in time to effect the change to the next state.
In that case, the machine has not met the criticalpath requirement. State changes in the finite-state machine. In technical jargon this is known as critical-path violation. Critical path is defined as the chain of gates in the longest slowest path through the logic, which causes a signal to take a certain length of time to propagate from the input to the output. Often times, an additional state or states is inserted to assure that every transition proceeds in an orderly and timely fashion.
This is known as pipelining. A diagram of a pipelined system is shown in Fig Several clock cycles may be needed in order for the signal to propagate through various stages of a computer system.
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Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic. The only book to be entirely devoted to clocking Clocking has become one of the most important topics in the field of digital system design AMoreProvides the only up-to-date source on the most recent advances in this often complex and fascinating topic. The only book to be entirely devoted to clocking Clocking has become one of the most important topics in the field of digital system design A must have book for advanced circuit engineers. Bring this list on your next trip to the supermarket, select something new, and prepare it as This recipe combines other healthy superstar ingredients, too:. Contemporary Review Classic Reprint currently available at xtmplzmcools.
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All rights reserved. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section or of the United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation.
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